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motorola semiconductor technical data ? motorola, inc. 2004 order this document by MPC9608 1:10 lvcmos zero delay clock buffer the MPC9608 is a 3.3 v compatible, 1:10 pll based zero-delay buffer. with a very wide frequency range and low output skews the MPC9608 is targeted for high performance and mid-range clock tree designs. features ? 1:10 outputs lvcmos zero-delay buffer ? single 3.3 v supply ? supports a clock i/o frequency range of 12.5 to 200 mhz ? selectable divide-by-two for one output bank ? synchronous output enable control (clk_stop) ? output tristate contro l (output high impedance) ? pll bypass mode for low freq uency system test purpose ? supports networking, telecommunica tions and computer applications ? supports a variety of microprocessors and controllers ? compatible to powerquicc i and ii ? ambient temperature range -40 c to +85 c ? 32-lead pb-free package available functional description the MPC9608 uses an internal pll and an external feedback path to lock its low-skew clock output phase to the reference clock phase, providing virtually zero propagation delay. this enables nested cl ock designs with near-zero insertion delay. designs using the MPC9608 as pll fanout buffer will show significantly lower clock skew th an clock distributions develop ed from traditional fanout buffers. the device offers one referenc e clock input and two banks of 5 outputs for clock fanout. the i nput frequency and phase is reproduced by the pll and provided at the outputs. a selectable frequency divider sets the bank b output s to generate either an identical copy of the bank a clocks or one half of the bank a clock frequency. both output banks remain s yn- chronized to the input reference for both bank b configurations. outputs are only disabled or enabled when t he outputs are already in logic low state (clk_stop). for system test and diagnosis, the MPC9608 outputs can also be set to high-impedance state by connecting oe to logic high level. additionally, the device provides a pll bypass mode for low frequency test purpose. in pll bypass m ode, the minimum frequency and stat ic phase offset specificati on do not apply. clk_stop and oe do not affect the pll feedback out put (qfb) and down stream clocks can be disabled without the internal pll losing lock. the MPC9608 is fully 3.3 v compatible and requires no external components for the internal pll. all inputs accept lvcmos sig- nals while the outputs provide lvcmos compatible levels with the c apability to drive terminated 50 ? transmission lines on the inci- dent edge. for series terminated transmission lines, each of the mp c9608 outputs can drive one or tw o traces giving the devices an effective fanout of 1:20. the device is packaged in a 7x7 mm 2 32-lead lqfp package. fa suffix 32-lead lqfp package case 873a MPC9608 low voltage 3.3 v lvcmos 1:10 zero-delay clock buffer ac suffix 32 lead lqfp package-pb-free case 873a rev 2 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MPC9608 2 timing solutions figure 1. MPC9608 logic diagram pll fb_in qa0 qa1 qa2 qa3 qa4 ref fb cclk qfb 2 2 qb0 qb1 qb2 qb3 qb4 bank a bank b pll feedback bsel clk_stop vco cclk stop f_range[0:1] 00: 100-200 mhz 01: 50-100 mhz 10: 25- 50 mhz 11:12.5- 25 mhz 25k 25k 25k 25k 25k 25k 25k oe pll_en vcc qa4 qa3 qa2 gnd qa1 qa0 vcc qb4 qb3 qb2 gnd qb1 gnd clk_stop bsel vcc f_range0 f_range1 oe gnd gnd cclk pll_en vcca vcc fb_in qfb gnd 25 26 27 28 29 30 31 32 15 14 13 12 11 10 9 12345678 24 23 22 21 20 19 18 17 16 MPC9608 vcc qb0 vcc figure 2 . MPC9608 32-lead package pinout (top view) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MPC9608 timing solutions 3 table 1. pin configuration pin i/o type function cclk input lvcmos pll reference clock signal fb_in input lvcmos pll feedback signal input, connect to a qfb output f_range[0:1] input lvcmos pll frequency range select bsel input lvcmos frequency divider select for bank b outputs pll_en input lvcmos pll enable/disable oe input lvcmos output enable/disable (high-impedance tristate) clk_stop input lvcmos synchr onous clock enable/stop qa0-4, qb0-4 output lvcmos clock outputs qfb output lvcmos pll feedback signal output. connect to fb_in gnd supply ground negative power supply vcca supply vcc pll positive power s upply (analog power supply). the MPC9608 requires an external rc filter for the analog power supply pin v cca. refer to the applications information section for details. vcc supply vcc positive powe r supply for i/o and core table 2. function table control default 0 1 f_range[0:1] 00 pll frequency range. refer to table 3 ?clock frequency configuration for qfb connected to fb_in? bsel 0 f qb0-4 = f qa0-4 f qb0-4 = f qa0-4 2 clk_stop 0 outputs enabled outputs synchronously stopped in logic low state oe 0 outputs enabled (active) outputs disabled (high-impedance state), independent on clk_stop. applying oe = 1 and pll_en = 1 resets the device. the pll feedback output qfb is not affected by oe . pll_en 0 normal operation mode with pll enabled. test mode with p ll disabled. cclk is substituted for the internal vco output. MPC9608 is fully static and no minimum frequency limit applies. all pll related ac characteristics are not applicable. applying oe = 1 and pll_en = 1 resets the device. table 3. clock frequency configuration for qfb connected to fb_in f_range[0] f_range[1] bsel f ref (cclk) range [mhz] qa0-qa4 qb0-b4 qfb ratio f qa0-4 [mhz] ratio f qb0-4 [mhz] 0 0 0 100.0 ? 200.0 f ref 100.0 ? 200.0 f ref 100.0 ? 200.0 f ref 001 f ref 2 50.0 ? 25.0 f ref 0 1 0 50.0 ? 100.0 f ref 50.0 ? 100.0 f ref 50.0 ? 100.0 f ref 011 f ref 2 25.0 ? 50.0 f ref 1 0 0 25.0 ? 50.0 f ref 25.0 ? 50.0 f ref 25.0 ? 50.0 f ref 101 f ref 2 12.5 ? 25.0 f ref 1 1 0 12.5 ? 25.0 f ref 12.5 ? 25 f ref 12.5 ? 25.0 f ref 111 f ref 2 6.25 ? 12.5 f ref f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MPC9608 4 timing solutions a. absolute maximum continuos ratings are those maximum values beyond which damage to the device may occur. exposure to these co nditions or conditions beyond those indicated may adv ersely affect device reliabi lity. functional operation at absolute-maximum-rated co nditions is not implied. a. the MPC9608 is capable of driving 50 ? transmission lines on the incident edge. each output drives one 50 ? parallel terminated transmission line to a termination voltage of v tt . alternatively, the devic e drives up to two 50 ? series terminated transmission lines. b. inputs have pull-down resistors affecting the input current. table 4. general specifications symbol characteristics min typ max unit condition v tt output termination voltage v cc 2v mm esd protection (machine model) 200 v hbm esd protection (human body model) 2000 v lu latch-up immunity 200 ma c pd power dissipation capacitance 10 pf per output c in input capacitance 4.0 pf inputs table 5. absolute maximum ratings a symbol characteristics min max unit condition v cc supply voltage -0.3 3.6 v v in dc input voltage -0.3 v cc +0.3 v v out dc output voltage -0.3 v cc +0.3 v i in dc input current 20 ma i out dc output current 50 ma t s storage temperature -65 125 c table 6. dc characteristics (v cc = 3.3 v 5%, t a = -40 to 85 c) symbol characteristics min typ max unit condition v ih input high voltage 2.0 v cc +0.3 v lvcmos v il input low voltage 0.8 v lvcmos v oh output high voltage 2.4 v i oh = -24 ma a v ol output low voltage 0.55 0.30 v v i ol = 24 ma i ol = 12 ma z out output impedance 14 ? 17 ? i in input current b 200 av in =v cc or gnd i cca maximum pll supply current 4.0 8.0 ma v cca pin i ccq maximum quiescent supply current 1.0 4.0 ma all v cc pins f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MPC9608 timing solutions 5 a. ac characteristics apply for par allel output termination of 50 ? to v tt . b. pll mode requires pll_en = 0 to enab le the pll and zero-delay operation. c. in bypass mode, the MPC9608 divides the input reference clock. d. applies for bank a and for bank b if bsel = 0. if bsel = 1, the mi nimum and maximum output frequency of bank b is divided by two. e. calculation of reference duty cycle limits: dc ref, min =t pw, min * f ref *100% and dc ref, max = 100% ? dc ref, min . for example, at f ref = 100 mhz the input duty cycl e range is 20% < dc < 80%. f. -3 db point of pll transfer characteristics. table 7. ac characteristics (v cc = 3.3 v 5%, t a = -40 to 85 c) a symbol characteristics min typ max unit condition f ref input reference frequency in pll mode b f_range = 00 f_range = 01 f_range = 10 f_range = 11 input reference frequency in pll bypass mode c 100 50 25 12.5 0 200 100 50 25 200 mhz mhz mhz mhz mhz f max output frequency d f_range = 00 f_range = 01 f_range = 10 f_range = 11 100 50 25 12.5 200 100 50 25 mhz mhz mhz mhz bsel = 0 bsel = 0 bsel = 0 bsel = 0 t pw, min reference input pulse width e 2.0 ns t r , t f cclk input rise/fall time 1.0 ns 0.8 v to 2.0 v t ( ? ) propagation delay (spo) cclk to fb_in f ref = 100 mhz and above f ref = 12.5 mhz to 100 mhz -175 -1.75% of t per +175 +1.75% of t per ps ps pll locked t sk(o) output-to-output skew within a bank bank-to-bank all outputs, inluding qfb 80 100 150 ps dc output duty cycle 45 50 55 % t r , t f output rise/fall time 0.1 1.0 ns 0.55 v to 2.4 v t plz, hz output disable time 10 ns t pzl, lz output enable time 10 ns t jit(cc) cycle-to-cycle jitter 150 ps bsel = 0 t jit(per) period jitter 150 ps bsel = 0 t jit( ? ) i/o phase jitter rms (1 ) 125 ps bsel = 0 bw pll closed loop bandwidth f f_range = 00 f_range = 01 f_range = 10 f_range = 11 7 ? 15 2 ? 7 1 ? 3 0.5 ? 1.3 mhz mhz mhz mhz t lock maximum pll lock time 10 ms f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MPC9608 6 timing solutions applications information power supply filtering the MPC9608 is a mixed analog/digital product. its analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. random noise on the v cca (pll) power supply impacts the device characteris- tics, for instance i/o jitter. the MPC9608 provides separate power supplies for the output buffers (v cc ) and the phase-locked loop (v cca ) of the device. the purpose of this de- sign technique is to isolate the high switching noise digital out- puts from the relatively sensit ive internal analog phase-locked loop. in a digital system environmen t where it is mo re difficult to minimize noise on the power supplies a second level of isolation may be required. the simple but effective form of isolation is a power supply filter on the v cca pin for the MPC9608. figure 3 illustrates a typical power supp ly filter scheme. the MPC9608 frequency and phase stability is most susceptible to noise with spectral content in the 100 khz to 20 mhz range. therefore the filter should be designed to target this range. the key parame- ter that needs to be met in the fi nal filter design is the dc volt- age drop across the seri es filter resistor r f . from the data sheet the i cca current (the current sourced through the v cca pin) is typically 4 ma (8 ma maximum), assuming that a mini- mum of 3.125 v must be maintained on the v cca pin. the re- sistor r f shown in figure 3 ?v cca power supply filter? must have a resistance of 9 ? 10 ? (v cc = 3.3 v) to meet the voltage drop criteria. the minimum values for r f and the filter capacitor c f are defined by the required filter char acteristics: the rc filter should provide an attenuation greater than 40 db for noise whose spectral content is above 100 khz. in the example rc filter shown in figure 3 ?v cca power supply filter?, the filter cut-off frequency is around 3-5 khz and the noise attenuation at 100 khz is better than 42 db. as the noise frequency crosses the series resonant point of an individual capacitor, its overall impedance begins to look inductive and thus increases with increasing frequency. the parallel capacitor combination shown ensures that a low imped- ance path to ground exists for frequencies well above the band- width of the pll. although the MPC9608 has several design features to minimize the susceptibility to power supply noise (isolated power and grounds and fully differential pll), there still may be applications in which overall performance is being degraded due to system power su pply noise. the power supply filter schemes discussed in this section should be adequate to eliminate power supply noise rela ted problems in most designs. using the MPC9608 in zero-delay applications nested clock trees are typical applications for the MPC9608. designs using the MPC9608, as lvcmos pll fanout buffer with zero insertion delay, will show significantly lower clock skew than clock distributions developed from cmos fanout buffers. the ex ternal feedback option of the MPC9608 clock driver allows for its use as a zero delay buffer. by using the qfb output as a feedback to the pll the propagation delay through the device is virtually eliminated. the pll aligns the feedback cl ock output edge with the clock input reference edge resulting in a near zero delay through the device. the maximum insertion delay of the device in zero-delay applications is me asured between the reference clock input and any output. this effective delay consists of the static phase offset, i/o jitter (p hase or long-term jitter), feedback path delay and the output-to-output skew error relative to the feedback output. calculation of part-to-part skew the MPC9608 zero delay buffer supports applications where critical clock signal timing can be maintained across sev- eral devices. if the reference clock inputs of two or more MPC9608 are connected together, the maximum overall timing uncertainty from the common cclk input to any output is: t sk(pp) = t ( ? ) + t sk(o) + t pd, line(fb) + t jit( ? ) . cf this maximum timing uncertainty consists of 4 compo- nents: static phase offset, ou tput skew, feedback board trace delay, and i/o (phase) jitter: figure 3 . v cca power supply filter v cca v cc MPC9608 10 nf r f = 9-10 ? for v cc = 3.3 v c f 33...100 nf r f v cc c f = 1 f for v cc = 3.3 v figure 4 . MPC9608 maximum device-to-device skew t pd,line(fb) t jit( ? ) + t sk(o) -t ( ? ) +t ( ? ) t jit( ? ) + t sk(o) t sk(pp) max. skew cclk common qfb device 1 any q device 1 qfb device2 any q device 2 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MPC9608 timing solutions 7 due to the statistica l nature of i/o jitter, an rms value (1 ) is specified. i/o jitter numbers for other confidence factors (cf) can be derived from table 8. the feedback trace delay is determined by the board layout and can be used to fine-tune the effective delay through each device. in the following example calculation a i/o jitter confi- dence factor of 99.7% ( 3 ) is assumed, resu lting in a worst case timing uncertainty from input to any output of -295 ps to 295 ps 1 relative to cclk: t sk(pp) = [-100 ps...100 ps] + [-150 ps...150 ps] + [(15 ps . -3)...(15 ps . 3)] + t pd, line(fb) t sk(pp) = [-295 ps...295 ps] + t pd, line(fb) driving transmission lines the MPC9608 clock driver was designed to drive high speed signals in a terminated transmission line environment. to provide the optimum flexibility to the user th e output drivers were designed to exhibit the lowest impedance possible. with an output impedance of less than 20 ? the drivers can drive ei- ther parallel or series terminated transmission lines. for more information on transmission lines the reader is referred to mo- torola application note an1091. in most high performance clock networks point-to-point distributio n of signals is the method of choice. in a point-to-point scheme either series terminated or parallel terminated transmission lines can be used. the parallel technique terminates the signal at the end of the line with a 50 ? resistance to v cc 2. this technique draws a fairly high level of dc current and thus only a single terminated line can be driven by each output of the MPC9608 clock driver. for the series terminated case however there is no dc current draw, thus the outputs can drive multiple series terminated lines. figure 5 ?single versus dual transmission lines? illustrates an output driving a single series terminated line versus two series terminated lines in parallel. when taken to its extreme, t he fanout of the MPC9608 clock driver is effectively doubled due to its capability to drive multiple lines. the waveform plots in figure 6 ?single versus dual line termination waveforms? show the simulation results of an out- put driving a single line versus two lines. in both cases the drive capability of the MPC9608 output buffer is more than sufficient to drive 50 ? transmission lines on the incident edge. from the delay measurements in the simulations a delta of only 43 ps ex- ists between the two differently loaded outputs. this suggests that the dual line driving need not be used exclusively to main- tain the tight output-to-output skew of the MPC9608. the output waveform in figure 6 ?single versus dual line termination waveforms? shows a step in the waveform. this step is caused by the impedance mismatch seen looking into the driver. the parallel combination of the 36 ? series resistor plus the output impedance does not match the parallel combination of the line impedances. the voltage wave launched down the two lines will equal: v l =v s ( z 0 (r s +r 0 +z 0 )) z 0 = 50 ? || 50 ? r s =36 ? || 36 ? r 0 =14 ? v l = 3.0 ( 25 (18 + 17 + 25)) =1.31 v at the load end the voltage will double to 2.6 v due to the near unity reflection coefficient. it will then increment towards the quiescent 3.0 v in steps separ ated by one round trip delay (in this case 4.0 ns). table 8. confidence facter cf cf probability of clock edge within the distribution 1 0.68268948 2 0.95449988 3 0.99730007 4 0.99993663 5 0.99999943 6 0.99999999 1. skew data are designed targets and pending device specifcations. figure 5 . single versus dual transmission lines 14 ? in MPC9608 output buffer r s = 36 ? z o = 50 ? outa 14 ? in MPC9608 output buffer r s = 36 ? z o = 50 ? outb0 r s = 36 ? z o = 50 ? outb1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MPC9608 8 timing solutions since this step is well above the threshold region, it will not cause any false clock triggering; however, designers may be uncomfortable with unwanted reflections on the line. to better match the impedances when driving multiple lines the situation in figure 7 ?optimized dual line termination? should be used. in this case the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance the line impedance is perfectly matched. figure 6 . single versus dual waveforms time (ns) v o lta g e ( v ) 3.0 2.5 2.0 1.5 1.0 0.5 0 2 4 6 8 10 12 14 outb t d = 3.9386 outa t d = 3.8956 in figure 7 . optimized dual line termination 14 ? MPC9608 output buffer r s = 22 ? z o = 50 ? r s = 22 ? z o = 50 ? 14 ? + 22 ? || 22 ? = 50 ? || 50 ? 25 ? = 25 ? figure 8 . cclk MPC9608 ac test reference for v cc = 3.3 v pulse generator z = 50 ? r t = 50 ? z o = 50 ? r t = 50 ? z o = 50 ? MPC9608 dut v tt v tt f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MPC9608 timing solutions 9 figure 9 . output-to-output skew t sk(o) the pin-to-pin skew is defined as the worst case difference in propa- gation delay between any similar del ay path within a single device. v cc v cc 2 gnd v cc v cc 2 gnd t sk(o) v cc v cc 2 gnd v cc v cc 2 gnd t ( ? ) cclk fb_in figure 10 . propagation delay (t pd , static phase offset) test reference the time from the pll controlled edge to the non controlled edge, di- vided by the time between pll cont rolled edges, expressed as a per- centage. v cc v cc 2 gnd t p t 0 dc = t p /t 0 x 100% figure 11 . output duty cycle (dc) figure 12. i/o jitter the deviation in t 0 for a controlled edge with respect to a t 0 mean in a random sample of cycles. t jit( ? ) = | t 0 - t 1 mean | cclk fb_in figure 13. cycle-to-cycle jitter the variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs. t n t jit(cc) = | t n -t n + 1 | t n + 1 figure 14. period jitter the deviation in cycle time of a sig nal with respect to the ideal period over a random sample of cycles. t jit(per) = | t n - 1 / f 0 | t 0 figure 15. output transition time test reference t f t r v cc =3.3 v 2.4 0.55 figure 16. setup and hold time (t s , t h ) test reference v cc gnd t s cclk clk_stop v cc gnd t h v cc 2 v cc 2 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MPC9608 10 timing solutions 12 ref dim min max millimeters a a1 7.00 bsc a2 0.80 bsc b 9.00 bsc b1 0.30 0.40 c 0.09 0.20 c1 0.09 0.16 d d1 e e e1 l l1 1.00 ref r1 0.08 0.20 r2 s 1 1.40 1.60 0.05 0.15 1.35 1.45 0.30 0.45 0.08 --- 0? 7? 9.00 bsc 7.00 bsc 0.50 0.70 q q 0.20 ref d1 d/2 e e1 1 8 9 17 25 32 d1/2 e1/2 e/2 4x d 7 a d b a-b 0.20 h d 4x a-b 0.20 c d 6 6 4 4 detail g pin 1 index detail ad r r2 ? (s) l (l1) 0.25 gauge plane a2 a a1 ( 1?) 8x r r1 e seating plane detail ad 0.1 c c 32x 28x h detail g f f e/2 a, b, d 3 section f-f base c1 c b b1 metal a-b m 0.20 d c 5 8 plating notes: 1. dimensions are in millimeters. 2. interpret dimensions and tolerances per asme y14.5m, 1994. 3. datums a, b, and d to be determined at datum plane h. 4. dimensions d and e to be determined at seating plane c. 5. dimension b does not include dambar protrusion. allowable dambar protrusion shall not cause the lead width to exceed the maximum b dimension by more than 0.08-mm. dambar cannot be located on the lower radius or the foot. minimum space between protrusion and adjacent lead or protrusion: 0.07-mm. 6. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25-mm per side. d1 and e1 are maximum plastic body size dimensions including mold mismatch. 7. exact shape of each corner is optional. 8. these dimensions apply to the flat section of the lead between 0.1-mm and 0.25-mm from the lead tip. outline dimensions fa suffix lqfp package ac suffix lqfp package-pb-free case 873a-02 issue a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MPC9608 11 timing solutions notes notes f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
how to reach us: usa/europe/locations not listed: japan: motorola japan ltd.; sps, technical information center motorola literature distribution 3-20-1 minami-azabu. minato-ku, tokyo 106-8573, japan p.o. box 5405, denver, colorado 80217 81-3-3440-3569 1-800-521-6274 or 480-768-2130 asia/pacific: motorola semiconductors h.k. ltd.; silicon harbour centre 2 dai king street, tai po industrial estate, tai po, n.t., hong kong 852-26668334 home page: http://motorola.com/semiconductors MPC9608 information in this document is provided solely to enable system and software implem enters to use motorola products. there are no express or implied copyright licenses granted hereunder to desig n or fabricate any integrated circuits or integrated circuits based on the informa tion in this document. motorola reserves the right to make changes without further noti ce to any products herein. motorola makes no warranty, represen tation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters which may be provided in motorola data sheets and/or s pecifications can and do vary in different applications and actual performance may var y over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola pro ducts are not designed, intended, or authorized for use as compon ents in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and di stributors harmless against all claims, costs, damages, and expenses , and reasonable attorney fees arising out of, directly or indirectly, any claim of persona l injury or death associated with such unintended or unauthorized use, even if such claim a lleges that motorola was negligent regarding the design or manufa cture of the part. motorola and the stylized m logo are registered in the us patent and trademark office. all other product or service names are t he property of their respective owners. ? motorola, inc. 2004 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .

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